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Course Description

This course provides the core knowledge and competencies of logic design, Boolean algebra, and essential Verilog and VHDL statements describing behavioural functions such as counters and other finite state machines. Participants master the ASIC design flow from examples of logic and circuit design analysis, computer abstractions, and performance metrics.
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Course Sections

Class Number
5538
Type
LAB
Dates
Jan 13, 2020 to Apr 18, 2020
Delivery Options
Online  
Compulsory Fees
Domestic Fee non-credit $869.28 Click here to get more information
International Fee non-credit $0.00 Click here to get more information