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Course Description

This course provides the core knowledge and competencies of logic design, Boolean algebra, and essential Verilog and VHDL statements describing behavioural functions such as counters and other finite state machines. Participants master the ASIC design flow from examples of logic and circuit design analysis, computer abstractions, and performance metrics.

Notes

This course is fully online and asynchronous, meaning you typically will not have to be online at specific times. You will engage in course-related activities through online tools such as announcements, discussions, and email. Your course learning will be based on weekly module content and activities that you can go through independently. Note: there are still deadlines for assignment submissions, and you may be expected to participate in discussion board interactions with your peers on a regular basis. 
 
Your instructor may also include occasional scheduled sessions for Q&As and other discussion activities, using web conferencing tools such as Zoom and Google Meet. More details will be included in your course outline available on the first day of class.
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Course Sections
Class Number
1831
Type
LAB
Dates
May 03, 2021 to Jul 30, 2021
Delivery Options
Online  
Fees
Domestic Fee non-credit $948.20 Click here to get more information
International Fee non-credit $0.00 Click here to get more information